Need often arises to operate a plurality of devices as a single unit, in precise step with each other. It is therefore necessary to synchronize the operation of the plurality of devices. The slowest of the devices is the limiting factor on the speed of operation of the synchronized devices, and all devices must be synchronized to the slowest one.
For example, in the computer field, first-in first-out buffer memories (FIFOs) are commonly utilized for interfacing inputs and outputs of a device to another device or to a communication link. While the width of a communication link or of a device's input and output port can vary widely, FIFOs are commonly available in a standard width, for example of four bits. Hence, for purposes of interfacing a port or link wider than the standard FIFO width, a plurality of FIFOs commonly must be used in an array configuration and operated in step. To assure proper operation of the FIFO array, the FIFOs must be synchronized to the operation of the slowest of the FIFOs, both in terms of commencing operation and of terminating operation.
The prior art has proposed schemes for synchronizing the operation of the FIFOs. However, certain proposed schemes have been found not to be operational, and those that are functional have been found to introduce significant delay into the operation of the FIFOs. But, as the speed of operation of computing and communication systems increases, the operational speed of such FIFO arrays often becomes the limiting factor on system operation, and the delays caused by the prior art synchronizing mechanisms become unacceptable in terms of system performance.